In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs), are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
In view of the above, there is a need for providing integrated semiconductor devices that are formed upon a substrate having different crystal orientations that provide optimal performance for a specific device. A need also exists to provide a method to form such an integrated semiconductor device in which both the nFETs and the pFETs are formed on a silicon-on-insulator substrate having different crystallographic orientations in which the semiconducting layers that the devices are built upon are substantially coplanar and have substantially the same thickness.
Prior art approaches to this problem are shown in FIGS. 1-3. Specifically, FIGS. 1A-1F show the steps of a prior art epitaxial growth method described in U.S. Ser. No. 10/250,241 for making a planar hybrid orientation substrate comprising one or more regions of a first single-crystal semiconductor disposed on bulk silicon, said first semiconductor having a first orientation; and
one or more regions of a second single-crystal semiconductor disposed on a BOX layer, said second semiconductor having a second orientation different from the first.
FIG. 1A shows an initial semiconductor-on-insulator (SOI) substrate 10 comprising a base semiconductor substrate layer 20 having a first orientation; a dielectric or buried oxide layer 30; an SOI layer 40 having a second orientation different from the first; and an optional surface dielectric masking/passivation layer 50. Layers 20, 30, and 40 of the initial SOI substrate 10 are typically formed by bonding two different semiconductor wafers together. The base semiconductor substrate layer 20 may optionally be substituted with any combination of semiconductor and insulating layers provided that an upper surface portion of the base semiconductor substrate includes a top layer of a single crystal semiconductor.
FIG. 1B shows the structure of FIG. 1A after one or more openings 60 are formed in layers 50, 40, and 30 to expose a surface of the base semiconductor substrate 20. As shown in FIG. 1C, sidewall spacers 70 may be formed on the exposed sidewalls of the openings 60. Next, a semiconductor material 80 having the same crystallographic orientation as that of the base semiconductor substrate 20 is epitaxially grown in the opening 60 on exposed surfaces of layer 20 and thereafter an optional planarization step can be utilized to form the structure of FIG. 1D. FIG. 1E shows the structure of FIG. 1D after additional planarization steps to remove the masking/passivation layer 50, and FIG. 1F shows the structure of FIG. 1E after optional formation of shallow trench isolation regions 90.
A drawback of the method described above and illustrated in FIGS. 1A-1F is that the processing leaves only one of the semiconductor orientations disposed on a BOX. FIGS. 2A-2F show the additional masking and SIMOX (separation by implanted oxygen) steps described in U.S. application Ser. No. 10/634,446 that can be applied to the structure of FIG. 1D, 1E, or 1F to selectively form a BOX layer in the one or more regions of the epitaxially grown semiconductor 80. FIG. 2A shows the structure of FIG. 1D after formation of a patterned mask 100 with a mask opening 110. FIG. 2B shows the structure of FIG. 2A being implanted with oxygen ions 120 to form an oxygen-rich silicon layer 130 and a damaged single crystal semiconductor region 140 in the semiconductor layer 80 exposed by the mask opening 110. FIG. 2C shows the structure of FIG. 2B after a high temperature annealing in an oxygen-containing ambient has converted the oxygen-rich silicon layer 130 into a buried oxide layer 150, and the damaged semiconductor region 140 into a device-quality semiconductor layer 140′. A surface oxide layer 170 also forms during the high temperature annealing step. FIG. 2D shows the structure of FIG. 2C after removal of the masking layers 50 and 100, removal of the surface oxide layer 170, and partial removal of the sidewall spacers 70. FIG. 2E shows the structure of FIG. 2D after optional formation of shallow trench isolation regions 190.
A drawback of the approach described above and illustrated in FIGS. 2A-2E is that it requires additional masking layers to protect the semiconductor layer 40 from the SIMOX implant and anneal. Use of such masking layers would typically require the additional steps of mask layer deposition, and lithographic alignment and patterning.
FIGS. 3A-3D outline an alternative amorphization/templated recrystallization (ATR) method described in U.S. Ser. No. 10/725,850 for making a planar hybrid orientation substrate having one or more regions of a first single-crystal semiconductor with a first orientation, and one or more regions of a second single-crystal semiconductor with a second orientation, where both first and second semiconductor regions are disposed on a BOX layer created by a SIMOX treatment applied to both semiconductor regions. FIG. 3A shows a bonded substrate 200 comprising a semiconductor substrate 210 having a first crystallographic orientation and a semiconductor layer 220 having a second orientation joined at a bonding interface 215. Selected regions of the substrate 200 are amorphized by a process such as ion implantation to produce the structure of FIG. 3B which includes an amorphized region 230 and non-amorphized regions 220′. The amorphized region 230 is then recrystallized with a process such as annealing to form a crystalline semiconductor 240 having the orientation of the semiconductor substrate 210, as shown in FIG. 3C. (Trenches or shallow trench isolation regions, not shown, would typically be formed at the boundaries between the amorphized and non-amorphized regions (230 and 220′, respectively) of the semiconductor layer 220 to prevent lateral templating.) A buried oxide region 250 is then formed under the differently oriented semiconductor regions 220′ and 240 by a SIMOX treatment applied to both semiconductor regions, as shown in FIG. 3D.
While the ATR approach illustrated in FIGS. 3A-3D is highly attractive, it (i) is less mature than epitaxial regrowth methods, and (ii) can be sensitive to oxides and contamination at the bonding interface 215.
In view of the above drawbacks with prior art approaches, there is a need for providing a method that is capable of creating a semiconductor substrate material having semiconductor layers of different crystallographic orientations that are substantially coplanar and of substantially the same thickness, yet are both located atop a buried insulating layer, e.g., a BOX layer.